- Fitxer VHDL per a la relització de la Pràctica 5

Continguts del fitxer

------------------------------------------------------------
-- Circuit : AND Gate
--
-- Note    : This VHDL program is a structural description
--         of the interactive AND Gate
--
--         If you are new to VHDL, then notice how the
--         program is designed: 1] first we declare the 
--         ENTITY, which is where we define the inputs
--         and the outputs of the circuit. 2] Second
--         we present the ARCHITECTURE, which is where
--         we describe the behavior and function of 
--         the circuit. 
------------------------------------------------------------

--import std_logic from the IEEE library
library ieee;
use ieee.std_logic_1164.all;

--ENTITY DECLARATION: name, inputs, outputs
entity Porta_AND is
   port( A, B : in std_logic;
            F : out std_logic);
end Porta_AND;

--FUNCTIONAL DESCRIPTION: how the AND Gate works
architecture func of Porta_AND is 
begin
   F <= A and B;
end func;
---------------------------------------------------------END
---------------------------------------------------------END