1. Introduction
- VHDL standard
- Examples: AND gate. Full Adder
- Testbench
- GHDL - gtkwave
2. Combinational
- Boolean functions
- Traffic light controller
- BCD to 7 segment decoder
3. Numerics
- Numerics basics
- Unsigned integers Assignments. Resizing unsigned integers
- Adding unsigned integers
- Adders, Fast-carry-chains. Carry lookahead
- VHDL adder. Adder with carry out
- Comparing unsigned integers Substracting unsigned integers
- Signed integers. Two’s complement
- Resizing signed integers
- Adding / substracting signed integers
- Abstract numeric types and conversions
4. Sequential basics
- D Flip-Flop. Process statements
- Clock enable. Synchronous and asynchronous reset
- Shift register. Testbench
- Counter. Testbench
5. Sequential systems: The Sequential Datapath and Control
Section Model
- Datapath
- Control section. Control signal generation
- State machines
- Simulation
6. Timing
- The Register Transfer Level Description
- Synchronous timing Critical Path
- Timing constraints
- Clock skew
- Outside connections. Asynchronous inputs. Metastability.
- Synchronizers. Slow inputs and bouncing
7. Memories
- Introduction
- Elementary Memory in VHDL
- Memory types
- Bidirectional ports. VHDL description. Testbench
- Memory with Tristate Ports
- Examples
8. Mini AVR in VHDL
- Processor basics. Architecture
- Instructions: NOP, LDI, ADC, MOV
- Registers
- Program ROM
- Status Register
- Control Unit
- ALU
- Completing the First Processor : NOP, LDI, ADC, MOV
9. Enhancing the processor
- Implementing the RJMP instruction
- Implementing the BREQ instruction
- Implementing the AND, OR, EOR instructions
- Adding some RAM
- Addressing RAM: Two-cycle instructions vs Indirect addressing
- Implementing the LD and ST instructions
- VHDL implementation. VHDL coding styles and effects on
- synthesis
- Implementing IO instructions: IN, OUT. Synchronizers.
- Implementing a timer
