Minimize the number of registers

Try to reduce, if possible, the number of registers used to synthesize the hardware description of the given vhd files. Any modification can be made in two ways: a) no change in the moment the signals are updated, even if it means delaying the updating of an already available signal and b) an advance in the moment at which the signal is updated (this is dangerous if this signal must be synchronized with another signal). Write comments in the code to mark your choice and its effects. You can compile all the vhdl files in your folder by running "ghdl -a *.vhd' or by using the Makefile that cleans the folder after the compilation.

Try the FPGA DE0-Nano simulation environment (ghdl+quartus)

Take as a start point this file, BP_v3.vhd, and try to reduce the number of registers that are used (as was made with the file BP_v1.vhd). Use the ghdl testbench to verify that now we lose no sample, i.e. each Goertzel window uses 205 samples each 205 clk_en (instead of using 205 samples each 206 clk_en). Then sinthesyze the design with quartus and compare this compilation report with the last one 234/60/6 (combinational functions/logic registers/9-bit multipliers). Don't forget to connect at least one bit of X_dtf to an output.